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Lines of code distribution across 4 owned repositories
11K
Total LOC
VHDL
5,040 lines
47.5%
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Shell
4,421 lines
41.6%
N/A
Verilog
1,155 lines
10.9%
N/A
π
Pi-Shaped Developer
π-shapedTwo strong pillars: VHDL & Shell
VHDL
Shell
Verilog
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Top Repositories
OS_EDA_Tools_Install
Open source EDA tools installment, including xschem, magic, ngspice, sky130 pdk.
13
13
Shell
SysGen_IP_Integration
Design your project in Simulink compatible System Generator for DSP (Vitis Model Composer), then generate HDL codes. Integrate your SysGen IP into Vivado.
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PWM_Deadtime_Generation_VHDL
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VHDL
PWM_Generation_VHDL
Simple PWM and deadtime generation & simulation in VHDL | Step by Step | Xilinx Vivado
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VHDL
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